1. Field of the Invention
Generally, the present disclosure relates to highly sophisticated integrated circuits including transistor elements having a double gate or triple gate architecture (FinFET).
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPUs, storage devices, ASICs (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements on a given chip area according to a specified circuit layout, wherein field effect transistors represent one important type of circuit element that substantially determines performance of the integrated circuits. Generally, a plurality of process technologies are currently practiced, wherein, for many types of complex circuitry including field effect transistors, MOS technology is currently one of the most promising approaches due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. During the fabrication of complex integrated circuits using, for instance, MOS technology, millions of transistors, e.g., N-channel transistors and/or P-channel transistors, are formed on a substrate including a crystalline semiconductor layer. A field effect transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, typically comprises so-called PN junctions that are formed by an interface of highly doped regions, referred to as drain and source regions, with a slightly doped or non-doped region, such as a channel region, disposed adjacent to the highly doped regions. In a field effect transistor, the conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed adjacent to the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends on, among other things, the dopant concentration, the mobility of the charge carriers and, for a planar transistor architecture, the distance between the source and drain regions, which is also referred to as channel length.
Presently, the vast majority of integrated circuits are based on silicon due to substantially unlimited availability, the well-understood characteristics of silicon and related materials and processes and the experience gathered during the last 50 years. Therefore, silicon will likely remain the material of choice for future circuit generations designed for mass products. One reason for the dominant importance of silicon in fabricating semiconductor devices has been the superior characteristics of a silicon/silicon dioxide interface that allows reliable electrical insulation of different regions from each other. The silicon/silicon dioxide interface is stable at high temperatures and, thus, allows the performance of subsequent high temperature processes, as are required, for example, for anneal cycles to activate dopants and to cure crystal damage without sacrificing the electrical characteristics of the interface.
For the reasons pointed out above, in field effect transistors, silicon dioxide is preferably used as a gate insulation layer that separates the gate electrode, frequently comprised of polysilicon or other metal-containing materials, from the silicon channel region. In steadily improving device performance of field effect transistors, the length of the channel region has been continuously decreased to improve switching speed and drive current capability. Since the transistor performance is controlled by the voltage supplied to the gate electrode to invert the surface of the channel region to a sufficiently high charge density for providing the desired drive current for a given supply voltage, a certain degree of capacitive coupling, provided by the capacitor formed by the gate electrode, the channel region and the silicon dioxide disposed therebetween, has to be maintained. It turns out that decreasing the channel length for a planar transistor configuration requires an increased capacitive coupling to avoid the so-called short channel behavior during transistor operation. The short channel behavior may lead to an increased leakage current and to a dependence of the threshold voltage on the channel length. Aggressively scaled transistor devices with a relatively low supply voltage, and thus reduced threshold voltage, may suffer from an exponential increase of the leakage current, while also requiring enhanced capacitive coupling of the gate electrode to the channel region. Thus, the thickness of the silicon dioxide layer has to be correspondingly decreased to provide the required capacitance between the gate and the channel region. The relatively high leakage current caused by direct tunneling of charge carriers through an ultra-thin silicon dioxide gate insulation layer may reach values for an oxide thickness in the range of 1-2 nm that may not be compatible with requirements for performance driven circuits.
For this reason, superior gate electrode structures have been developed in which new gate dielectric materials may be implemented, possibly in combination with additional electrode materials, in order to provide superior capacitive coupling between the gate electrode and the channel region, while at the same time maintaining the resulting leakage currents at a low level. To this end, so-called high-k dielectric materials are used, which are to be understood as dielectric materials having a dielectric constant of 10.0 and higher. For example, a plurality of metal oxides or silicates may be used, possibly in combination with conventional very thin dielectric materials, in order to obtain sophisticated high-k metal gate electrode structures. For example, in some well-established approaches, the gate electrode structures of planar transistors may be formed on the basis of well-established concepts, i.e., using conventional gate dielectrics and polysilicon material, wherein the sophisticated material systems are then incorporated in a very late manufacturing stage, i.e., prior to forming any metallization systems and after completing the basic transistor configuration by replacing the polysilicon material with the high-k dielectric material and appropriate gate electrode materials. Consequently, in any such replacement gate approaches, well-established process techniques and materials may be used for forming the basic transistor configurations, while, in a late manufacturing stage, i.e., after performing any high temperature processes, the sophisticated gate materials may be incorporated.
In view of further device scaling, possibly based on well-established materials, new transistor configurations have been proposed in which a “three dimensional” architecture is provided in an attempt to obtain a desired channel width, while at the same time superior controllability of the current flow through the channel region is preserved. To this end, so-called FinFETs have been proposed in which a thin sliver or fin of silicon is formed in a thin active layer of a silicon-on-insulator (SOI) substrate, wherein on both sidewalls and, if desired, on a top surface, a gate dielectric material and a gate electrode material are provided, thereby realizing a multiple gate transistor whose channel region may be fully depleted. Typically, in sophisticated applications, the width of the silicon fins is on the order of magnitude of 10-25 nm and the height thereof is on the order of magnitude of 30-40 nm. In some conventional approaches for forming FinFETs, the fins are formed as elongated device features, followed by the deposition of the gate electrode materials, possibly in combination with any spacers, and thereafter the end portions of the fins may be “merged” by epitaxially growing a silicon material, which may result in complex manufacturing processes, thereby also possibly increasing the overall external resistance of the resulting drain and source regions.
With reference to FIG. 1, a typical conventional SOI-based FinFET will now be described in order to explain the above-referenced problems in more detail. FIG. 1 schematically illustrates a perspective view of a semiconductor device 100 comprising a substrate 101, for example a silicon substrate, having formed thereon a buried insulating layer 102, whereas an initial silicon region or layer is already patterned into a plurality of silicon fins 110, which may thus represent a part of a FinFET transistor. The fins 110 may have a width 110W and a height 110H, as is specified above, in order to comply with packing density and transistor characteristics, such as full depletion and the like. Moreover, a gate electrode structure 160 is illustrated to be formed above and between the semiconductor fins 110. The gate electrode structure 160 may have any appropriate configuration, for instance in terms of a gate dielectric material, an electrode material and the like. Moreover, a spacer structure 161 is typically provided on sidewalls of the gate electrode structure 160. Thus, as discussed above, upon forming a gate electrode structure 160 above the patterned semiconductor fins 110, sophisticated patterning strategies have to be applied since it is typically necessary to etch a very straight profile while removing the polysilicon material or generally the electrode material from the top surface of the semiconductor fins 110. Moreover, the electrode material also has to be reliably removed at the bottom of the semiconductor fins, while also any electrode “spacers” have to be removed, which are temporarily formed due to the anisotropic nature of the corresponding gate etch process. Furthermore, since this highly complex “three-dimensional” etch process may have to be specifically adapted to FinFETs, it is typically not possible to use the same etch process for a planar field effect transistor, thereby requiring a redesign of any existing circuitry so as to avoid any two-dimensional transistors.
As already discussed above, the external resistance, indicated as R, may require an appropriate contact regime in order to provide a combined drain and source area of the semiconductor fin, which is conventionally accomplished by performing a selective epitaxial growth process in order to merge the corresponding end portions of the individual semiconductor fins 110. In this manner, metal silicide regions may be formed in the merged drain and source areas. On the other hand, however, upon merging the corresponding end portions, a parasitic capacitor is formed between the gate and the corresponding source/drain regions, as indicated by C, since here a gate-channel capacitance is not present. In this case, the resulting capacitance of the parasitic capacitor may reach significant values, thereby substantially affecting the overall transistor characteristics.
For these reasons, great efforts have been made in order to provide FinFETs on the basis of a self-aligned process strategy in which the semiconductor fins may be formed so as to be self-aligned with respect to a gate electrode structure. To this end, in a further step, the gate opening is patterned by complex lithography techniques so as to obtain a further mask, which may then define the lateral position and size of the semiconductor fins, which are subsequently formed on the basis of a complex patterning strategy. Thereafter, an appropriate dielectric material, such as silicon dioxide, is filled into the resulting structure in order to appropriately adjust the electrical effective height of the previously etched fins. Although at least some of the problems identified above regarding the conventional SOI-based FinFETs may be solved on the basis of these approaches, it appears that, upon further device scaling and in particular with the introduction of sophisticated gate electrode structures, the patterning sequence described above may no longer be compatible with any such further requirements.
For example, in sophisticated semiconductor devices, typically conventional gate dielectrics, such as silicon oxide-based materials, are replaced, at least partially, by so-called high-k dielectric materials, i.e., dielectric materials having a dielectric constant of 10.0 and higher, in order to increase the capacitive coupling between the gate electrode and the channel region while at the same time not unduly increasing the overall leakage currents. Upon introducing sophisticated high-k dielectric materials, typically the work function adjustment may require the incorporation of appropriate work function metal species, which may also typically be combined with the incorporation of a highly conductive electrode metal. Since the patterning of a corresponding complex gate electrode stack is very difficult, sophisticated process strategies have been developed in which a conventional gate electrode structure is formed and preserved until the basic transistor structure is completed and, in a later manufacturing stage, the placeholder materials, i.e., the polysilicon material, is removed and replaced by the desired sophisticated material system. Consequently, on the basis of any such sophisticated gate electrode structures, a further reduction of feature sizes of planar and three-dimensional transistors is possible. It turns out, however, that in particular the contacting of transistors of reduced lateral dimensions becomes increasingly difficult, for instance when the pitches between closely spaced neighboring gate electrode structures reach a range of 100 nm and significantly less. In this case, typical contact regimes, i.e., forming an interlayer dielectric material between and above the gate electrode structures, planarizing the material system and performing a complex contact patterning process so as to form openings that connect to the drain and source regions on the one side and to the gate electrode structures on the other side, may no longer be compatible with currently available lithography and patterning techniques.
Hence, “self-aligned” contact strategies have been developed in which a conductive contact material may be provided in a self-aligned manner with respect to the transistor length direction by, for instance, forming an opening in the interlayer dielectric material by a removal process that is selective with respect to the gate electrode structures. Thereafter, any appropriate conductive material may be deposited and planarized, thereby forming self-aligned contact elements that connect to the drain and source regions.
In sophisticated process strategies, a self-aligned contact regime may be combined with a replacement gate approach, wherein the actual replacement of the placeholder material may be performed after providing the self-aligned contact elements. Although this approach is very promising for further reducing the overall dimensions of planar transistors, it turns out, however, that a corresponding strategy may not be compatible with the formation of FinFETs, even if sophisticated process strategies may be applied as described above.
In view of the situation described above, the present disclosure relates to manufacturing techniques and semiconductor devices in which three-dimensional transistors or FinFETs may be provided with superior transistor characteristics, in particular to parasitic capacitance, while avoiding or at least reducing the effects of one or more of the problems identified above.